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crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 25 ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram features ? 8mb: 256k x 36 or 512k x 18 organizations 4mb: 128k x 36 or 256k x 18 organizations ? 0.25 micron cmos technology ? synchronous pipeline mode of operation with self-timed late write ? single differential hstl clock ? +2.5v power supply, ground, 1.5, 1.8v v ddq , and 0.90v v ref ? hstl input and output levels ? registered addresses, write enables, synchro- nous select, and data ins ? registered outputs ? common i/o ? asynchronous output enable ? synchronous power down input ? boundary scan using limited set of jtag 1149.1 functions ? byte write capability and global write enable ? 7 x 17 bump ball grid array package with sram jedec standard pinout and boundary scan order description the 4mb and 8mb sramsibm0436a41blab, ibm0418a41blab, ibm0418a81blab, and ibm0436a81blabare synchronous pipeline mode, high-performance cmos static random access memories that are versatile, wide i/o, and can achieve 3ns cycle times. differential k clocks are used to initiate the read/write operation and all internal operations are self-timed. at the rising edge of the k clock, all addresses, write-enables, sync select, and data ins are registered internally. data outs are updated from output registers off the next rising edge of the k clock. an internal write buffer allows write data to follow one cycle after addresses and controls. the device is operated with a single +2.5v power supply and is compatible with hstl i/o interfaces. .
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 25 crrh2519.07 12/13/00 x36 bga pinout (top view) 1234567 a v ddq sa sa nc sa sa v ddq b nc nc sa nc sa nc, sa(8mb) nc c nc sa sa v dd sa sa nc d dq23 dq19 v ss zq v ss dq10 dqb9 e dq20 dq26 v ss ss v ss dq12 dqb11 f v ddq dq22 v ss g v ss dq13 v ddq g dq18 dq24 sbwc nc sbwb dq15 dqb14 h dq25 dq21 v ss nc v ss dq17 dqb16 j v ddq v dd v ref v dd v ref v dd v ddq k dq34 dq35 v ss k v ss dq8 dq7 l dq32 dq33 sbwd k sbwa dq6 dq5 m v ddq dq31 v ss sw v ss dq4 v ddq n dq29 dq30 v ss sa0 v ss dq3 dq2 p dq27 dq28 v ss sa1 v ss dq1 dq0 r nc sa m1* v dd m2* sa nc t nc nc sa sa sa nc zz u v ddq tms tdi tck tdo nc v ddq note: * m1 and m2 are clock mode pins. for this application, m1 and m2 need to connect to v ss and v dd , respectively. x18 bga pinout (top view) 1234567 a v ddq sa sa nc sa sa v ddq b nc nc sa nc sa nc, sa(8mb) nc c nc sa sa v dd sa sa nc d dq9 nc v ss zq v ss dq1 nc e nc dq15 v ss ss v ss nc dq4 f v ddq nc v ss g v ss dq5 v ddq g nc dq16 sbwb nc nc nc dq8 h dq12 nc v ss nc v ss dq2 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dq11 v ss k v ss nc dq3 l dq13 nc nc k sbwa dq7 nc m v ddq dq17 v ss sw v ss nc v ddq n dq14 nc v ss sa0 v ss dq0 nc p nc dq10 v ss sa1 v ss nc dq6 r nc sa m1 v dd m2 sa nc t nc sa sa nc sa sa zz u v ddq tms tdi tck tdo nc v ddq note: * m1 and m2 are clock mode pins. for this application, m1 and m2 need to connect to v ss and v dd respectively.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 25 pin description sa0-sa18 address input sa0-sa18 for 512k x 18 sa0-sa17 for 256k x 36 sa0-sa17 for 256k x 18 sa0-sa16 for 128k x 36 g asynchronous output enable dq0-dq35 data i/o dq0-dq17 for 512k x 18 dq0-dq35 for 256k x 36 ss synchronous select k, k differential input register clocks m1, m2 clock mode inputs - selects single or dual clock operation. sw write enable, global v ref (2) hstl input reference voltage sbwa write enable, byte a (dq0-dq8) v dd power supply (+2.5v) sbwb write enable, byte b (dq9-dq17) v ss ground sbwc write enable, byte c (dq18-dq26) v ddq output power supply sbwd write enable, byte d (dq27-dq35) zz synchronous sleep mode tms,tdi,tck ieee 1149.1 test inputs (lvttl levels) zq output driver impedance control tdo ieee 1149.1 test output (lvttl level) nc no connect ordering information (these are all possible sorts; some may not be qualified.) part number organization speed leads ibm0418a41blab - 3 256k x 18 1.7ns access / 3.0ns cycle 7 x 17 bga ibm0418a41blab - 3f 256k x 18 1.8ns access / 3.3ns cycle 7 x 17 bga ibm0418a41blab - 3n 256k x 18 1.8ns access / 3.7ns cycle 7 x 17 bga ibm0418a41blab - 4 256k x 18 2.0ns access / 4.0ns cycle 7 x 17 bga ibm0418a41blab - 5 256k x 18 2.25ns access /5.0ns cycle 7 x 17 bga ibm0436a41blab - 3 128k x 36 1.7ns access / 3.0ns cycle 7 x 17 bga ibm0436a41blab - 3f 128k x 36 2.0ns access / 3.3ns cycle 7 x 17 bga ibm0436a41blab - 3n 128k x 36 1.8ns access / 3.7ns cycle 7 x 17 bga ibm0436a41blab - 4 128k x 36 2.0ns access / 4.0ns cycle 7 x 17 bga ibm0436a41blab - 5 128k x 36 2.25ns access /5.0ns cycle 7 x 17 bga ibm0418a81blab - 3 512k x 18 1.7ns access / 3.0ns cycle 7 x 17 bga ibm0418a81blab - 3f 512k x 18 1.8ns access / 3.3ns cycle 7 x 17 bga ibm0418a81blab - 3n 512k x 18 1.8ns access / 3.7ns cycle 7 x 17 bga ibm0418a81blab - 4 512k x 18 2.0ns access / 4.0ns cycle 7 x 17 bga ibm0418a81blab - 5 512k x 18 2.25ns access /5.0ns cycle 7 x 17 bga ibm0436a81blab -3 256k x 36 1.7ns access / 3.0ns cycle 7 x 17 bga ibm0436a81blab -3f 256k x 36 1.8ns access / 3.3ns cycle 7 x 17 bga ibm0436a81blab - 3n 256k x 36 1.8ns access / 3.7ns cycle 7 x 17 bga ibm0436a81blab -4 256k x 36 2.0ns access / 4.0ns cycle 7 x 17 bga ibm0436a81blab -5 256k x 36 2.25ns access /5.0ns cycle 7 x 17 bga
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 25 crrh2519.07 12/13/00 block diagram sbw row decode col decode read/wr amp doc_array0 sa0-sa18 k zz g sw ss dq0-dq35 reg reg sbw 2:1 mux doc_mux0 write1 add reg write0 add reg read add reg read write match match1 latch latch0 wr_buf1 wr_buf0 2:1 mux doc_mux1 2:1 mux doc_mux2 sbw0 sw0 sw1 reg reg doc_ dout0 reg reg ss1 ss0
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 25 sram features late write late write function allows for write data to be registered one cycle after addresses and controls. this feature eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. late write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. when a read cycle occurs after a write cycle, the address and write data information are stored tempo- rarily in holding registers. during the first write cycle preceded by a read cycle, the sram array will be updated with address and data from the holding registers. read cycle addresses are monitored to determine if read data is to be supplied from the sram array or the write buffer. the bypassing of the sram array occurs on a byte-by-byte basis. when only one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the sram array. mode control mode control pins m1 and m2 are used to select four different jedec-standard read protocols. this sram supports single clock, pipeline (m1 = v ss , m2 = v dd ). this datasheet only describes single clock pipeline functionality. mode control inputs must be set with power up and must not change during sram operation. this sram is tested only in the pipeline mode. sleep mode sleep mode is enabled by switching synchronous signal zz high. when the sram is in sleep mode, the out- puts will go to a high-z state and the sram will draw standby current. sram data will be preserved and a recovery time (t zzr ) is required before the sram resumes normal operation. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow for the sram to adjust its output driver impedance. the value of rq must be tbdx the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching is between 175 w and 350 w , with the tolerance described in programmable impedance output driver dc electrical char- acteristics on page 9. the rq resistor should be placed less than two inches away from the zq ball on the sram module. the total external capacitance (including wiring ) seen by the zq ball should be minimized (less than 7.5 pf). programmable impedance and power-up requirements periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. one evaluation occurs every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a time towards the optimum level. the output driver has 32 discrete binary weighted steps. the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high- z, therefore triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k clock to guarantee the proper update. there are no power-up requirements for the sram; however, to guarantee optimum output driver impedance after power up, the sram needs 4096 clock cycles followed by a low-z to high-z transition. power-up and power-down sequencing the power supplies need to be powered up in the following order: v dd , v ddq , v ref , and inputs. the power- down sequencing must be the reverse. v ddq can be allowed to exceed v dd by no more than 0.6v.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 25 crrh2519.07 12/13/00 clock truth table kzz ss sw sbw a sbwb sbwc sbwd dq (n) dq (n+1) mode l ? h llhx x xx x d out 0-35 read cycle all bytes l ? h ll l l hhh x d in 0-8 write cycle 1st byte l ? h lllhlhhx d in 9-17 write cycle 2nd byte l ? h ll l hh lh x d in 18-26 write cycle 3rd byte l ? h ll lhhhl x d in 27-35 write cycle 4th byte l ? h lllllllx d in 0-35 write cycle all bytes l ? h l l l h h h h x high-z abort write cycle l ? h l h x x x x x x high-z deselect cycle x h x x x x x x high-z high-z sleep mode output enable truth table operation (n, n+1) g (n) dq (n) dq (n+1) read l d out 0-35 d out 0-35 read h high-z high-z sleep (zz = h) x high-z high-z write ( sw = l) x x high-z deselect ( ss = h) x x high-z absolute maximum ratings item symbol rating units notes power supply voltage v dd -0.5 to 2.825 v 1 output power supply voltage v ddq -0.5 to 2.825 v 1 input voltage v in -0.5 to 4.3 v 1, 2 dq input voltage v dqin -0.5 to 2.825 v 1 operating temperature t a 0 to 85 c 1 junction temperature t j 110 c 1 storage temperature t stg -55 to +125 c 1 short circuit output current i out 25 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. excludes dq inputs.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 25 recommended dc operating conditions (t a = 0 to +85 c) parameter symbol min. typ. max. units notes supply voltage v dd 2.5 - 5% 2.5 2.5 + 5% v 1 output driver supply voltage v ddq 1.4 1.5, 1.8 1.9 v 1 input high voltage v ih v ref +0.1 v ddq + 0.3 v 1, 2 input low voltage v il -0.3 v ref - 0.1 v 1, 3 input reference voltage v ref 0.68 0.90 0.95 v 1, 6 clocks signal voltage v in - clk -0.3 v ddq + 0.3 v 1, 4 differential clocks signal voltage v dif - clk 0.1 v ddq + 0.6 v 1, 5 clocks common mode voltage v cm - clk 0.55 0.90 v 1 1. all voltages referenced to v ss . all v dd , v ddq , and v ss pins must be connected. 2. v ih (max)dc = v ddq + 0.3 v, v ih (max)ac = v ddq + 0.85 v (pulse width 4.0ns). 3. v il (min)dc = -0.3 v, v il (min)ac = -1.5 v (pulse width 4.0ns). 4. v in-clk speci?es the maximum allowable dc excursions of each differential clock (k, k). 5. v dif-clk speci?es the minimum clock differential voltage required for switching. 6. peak to peak ac component superimposed on v ref may not exceed 5% of v ref.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 25 crrh2519.07 12/13/00 dc electrical characteristics (t a = 0 to +85 c, v dd = 2.5v -5%, +5%) parameter symbol min. max. units notes average power supply operating current - x36 (i out = 0, v in = v ih or v il , zz & ss = v il ) i dd3 i dd3f i dd3n i dd4 i dd5 0.470 0.450 0.435 0.420 0.370 a 1, 3 average power supply operating current - x18 (i out = 0, v in = v ih or v il , zz & ss = v il ) i dd3 i i dd3f i dd3n i dd4 i dd5 0.450 0.430 0.415 0.400 0.350 a 1, 3 power supply standby current ( ss = v ih , zz = v il . all other inputs = v ih or v ih , i ih = 0) i sbss 150 ma 1 power supply sleep current (zz = v ih , all other inputs = v ih or v il , i out = 0) i sbzz 100 ma 1, 5 input leakage current, any input (except jtag) (v in = v ss or v dd ) i li -2 +2 m a output leakage current (v out = v ss or v dd , dq in high-z) i lo -5 +5 m a output high level voltage (i oh = -8ma) v oh v ddq -.4 v ddq v 2, 4 output low level voltage (i ol = +8ma) v ol v ss v ss +.4 v 2, 4 jtag leakage current (v in = v ss or v dd ) i lijtag -50 +10 m a 6 1. i out = chip output current. 2. minimum impedance output driver. 3. the numeric suffix indicates part operating at speed as indicated in ac characteristics on page 11: i.e., i dd3 indicates 3ns cycle time. 4. jedec standard jesd8-6 class 1 compatible. 5. when zz = high, spec is guaranteed at 75 c junction temperature. 6. for jtag inputs only. pbga thermal characteristics item symbol rating units thermal resistance junction to case r q jc 1 c/w capacitance (t a = 0 to +85 c, v dd = 2.5v -5%, +5%, f = 1mhz) parameter symbol test condition max units input capacitance c in v in = 0v 4pf data i/o capacitance (dq0-dq35) c out v out = 0v 4pf
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 25 ac input characteristics item symbol min max notes ac input logic high v ih (ac) v ref + 0.4 3 ac input logic low v il (ac) v ref - 0.4 3 clock input differential voltage v dif (ac) 0.7 2 v ref peak to peak ac voltage v ref (ac) 5% v ref (dc) 1 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref. 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input de?nition ?gure below. ac input de?nition programmable impedance output driver dc electrical characteristics (t a = 0 to +85 c, v dd = 2.5v -5%, +5%, v ddq = 1.8 v) parameter symbol min. max. units notes output high level voltage v oh v ddq / 2 v ddq v 1, 3 output low level voltage v ol v ss v ddq / 2 v 2, 3 1. i oh = 15% @ v oh = v ddq / 2 for: 175 w rq 350 w . 2. i ol = 15% @ v ol = v ddq / 2 for: 175 w rq 350 w . 3. parameter tested with rq = 250 w and v ddq = 1.8 v. v ih (ac) v ref v il (ac) vddq 2 ------------------ ? ?? rq 5 -------- -5 + ? ?? vddq 2 ------------------ ? ?? rq 5 -------- - ? ??
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 25 crrh2519.07 12/13/00 ac test conditions t( a = 0 to +85 c, v dd = 2.5v -5%, +5%, v ddq = 1.5, 1.8 v) parameter symbol conditions units notes output driver supply voltage v ddq 1.5, 1.8 v input high level v ih 1.5 v input low level v il 0.3 v input reference voltage v ref 0.75, 0.90 v differential clocks voltage v dif-clk 0.75 v clocks common mode voltage v cm-clk 0.75, 0.9 v input rise time t r 0.5 ns input fall time t f 0.5 ns i/o signals reference level (except k, c clocks) 0.9 v clocks reference level differential cross point v output load conditions 1, 2 1. see the ac test loading figure below. 2. parameter tested with rq = 250 w and v ddq = 1.8 v. ac test loading dq 50 w 50 w 5pf 50 w 25 w 50 w 5pf 0.75, 0.9v 0.9v 0.75, 0.9v
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 25 ac characteristics (t a = 0 to +85 c, v dd = 2.5v -5%, +5%) parameter symbol 33f 3n4 5 units notes min. max. min. max. min. max. min. max. min. max. cycle time t khkh 3.0 3.3 3.7 4.0 5.0 ns clock high pulse width t khkl 1.2 1.5 1.5 1.5 1.5 ns clock low pulse width t klkh 1.2 1.5 1.5 1.5 1.5 ns clock to output valid t khqv 1.7 1.8 1.8 2.0 2.25 ns 1 address setup time t avkh 0.5 0.5 0.5 0.5 0.5 ns 3 address hold time t khax 0.5 0.5 0.5 0.5 1.0 ns 3 sync select setup time t svkh 0.5 0.5 0.5 0.5 0.5 ns 3 sync select hold time t khsx 0.5 0.5 0.5 0.5 1.0 ns 3 write enables setup time t wvkh 0.5 0.5 0.5 0.5 0.5 ns 3 write enables hold time t khwx 0.5 0.5 0.5 0.5 1.0 ns 3 data in setup time t dvkh 0.5 0.5 0.5 0.5 0.5 ns 3 data in hold time t khdx 0.5 0.5 0.5 0.5 1.0 ns 3 data out hold time t khqx 0.5 0.5 0.5 0.5 0.5 ns 1 clock high to output high-z t khqz 2.25 2.25 2.25 2.25 2.5 ns 1 clock high to output active t khqx4 0.5 0.5 0.5 0.5 0.5 ns 1 output enable to high-z t ghqz 2.0 2.0 2.0 2.0 2.5 ns 1 output enable to low-z t glqx 0.5 0.5 0.5 0.5 0.5 ns 1 output enable to output valid t glqv 2.0 2.0 2.0 2.0 2.5 ns 1 output enable setup time t ghkh 0.5 0.5 0.5 0.5 0.5 ns 1, 2 output enable hold time t khgx 1.5 1.5 1.5 1.5 1.5 ns 1, 2 sleep mode setup time t zvkh 1.0 1.0 1.0 1.0 1.0 ns sleep mode hold time t khzx 1.0 1.0 1.0 1.0 1.0 ns sleep mode recovery time t zzr 200 200 200 200 200 ns 4 sleep mode enable time t zze 6 6.6 7.4 8 10 ns 1. see the ac test loading figure on page 10. 2. output driver impedance update speci?cations for g induced updates. write and deselect cycles will also induce output driver updates during high-z. 3. during normal operation, v ih , v il , t rise , and t fall of inputs must be within 20% of v ih , v il , t rise , and t fall of clock. 4. for t zzr <200ns, access time will be equal to twice t khqv .
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 25 crrh2519.07 12/13/00 read and deselect cycles timing diagram k ss sw g dq sa t khkh q1 q2 q3 q4 t khkl t khqv t avkh t khax t svkh t khsx t khwx t wvkh t khqx4 t khqv t ghqz t glqx a2 a1 t klkh t glqv t khqx t khqz a3 a3 a4
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 25 read write cycles timing diagram k ss sw g dq sa t khkh d2 q3 d4 t klkh t khkl t khqv t avkh t khax t svkh t khwx t wvkh t khqz t khqx4 sbw t dvkh t khdx t khqv q2 a1 a2 a2 a4 q1 notes: 1. d2 is the input data written in memory location a2. 2. q2 is output data read from the write buffer, as a result of address a2 being a match from the last write cycle address. t khwx t wvkh t wvkh t khwx t khwx t wvkh t dvkh t khdx t khsx t ghqz a3
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 25 crrh2519.07 12/13/00 synchronous sleep mode timing diagram k zz t khkh t zzr t zze addr dq t zvkh t zvkh t khqv q1 note: for t zzr < 200ns, access time will be equal to 2 x t khqv . a1 t avkh t khzx t khzx t khax
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 25 ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions intended to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee std. 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. signal list ? tck: test clock ? tms: test mode select ? tdi: test data in ? tdo: test data out. jtag dc operating characteristics (t a = 0 to +85 c) operates with jedec standard 8-5 (2.5v) logic signal levels parameter symbol min. typ. max. units notes jtag input high voltage v ih1 1.7 v dd +0.3 v 1 jtag input low voltage v il1 -0.3 0.8 v 1 jtag output high level v oh1 2.1 v 1, 2 jtag output low level v ol1 0.2 v 1, 3 1. all jtag inputs and outputs are lvttl compatible only. 2. i oh1 3 -|2ma| 3. i ol1 3 +|2ma|. jtag ac test conditions (t a = 0 to +85 c, v dd = 2.5v -5%, +5%) parameter symbol conditions units input pulse high level v ih1 3.0 v input pulse low level v il1 0.0 v input rise time t r1 2.0 ns input fall time t f1 2.0 ns input and output timing reference level 1.25 v
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 25 crrh2519.07 12/13/00 jtag ac characteristics (t a = 0 to +85 c, v dd = 2.5v -5%, +5%) parameter symbol min. max. units notes tck cycle time t thth 20 ns tck high pulse width t thtl 7ns tck low pulse width t tlth 7ns tms setup t mvth 4ns tms hold t thmx 4ns tdi setup t dvth 4ns tdi hold t thdx 4ns tck low to valid data t tlov 7ns 1 1. see the ac test loading figure on page 10. jtag timing diagram tck tms tdi tdo t thtl t tlth t thth t thmx t thdx t tlov t mvth t dvth
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 25 scan register de?nition register name bit size x18 bit size x36 instruction 3 3 bypass 1 1 id 32 32 boundary scan * 51 70 * the boundary scan chain consists of the following bits: ? 36 or 18 bits for data inputs, depending on x18 or x36 con?guration ? 18 bits for sa0 - sa14 in x36, 19 bits for sa0 - sa15 in x18 ? 4 bits for sbw a - sbwd in x36, 2 bits for sbw a and sbwb in x18 ? 9 bits for k, k, zq, ss, g, sw, zz, m1 and m2 ? 3 bits for place holders for 8 mb, 4bits for place holders for 4mb * k and k clocks connect to a differential receiver that generates a single-ended clock signal. this signal and its inverted value are used for boundary scan sampling. id register de?nition part field bit number and description revision number (31:28) device density and con?guration (27:18) vendor de?nition (17:12) manufacturer jedec code (11:1) start bit(0) 128k x 36 0111 011 010 1100 xxxxxx 000 101 001 00 1 256k x 18 0111 011 100 1011 xxxxxx 000 101 001 00 1 512k x 18 0111 101 111 0011 xxxxxx 000 101 001 00 1 256k x 36 0111 101 101 0100 xxxxxx 000 101 001 00 1
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 25 crrh2519.07 12/13/00 list of ieee 1149.1 standard violations ? 7.2.1.b, e ? 7.7.1.a-f ? 10.1.1.b, e ? 10.7.1.a-d ? 6.1.1.d instruction set code instruction notes 000 sample-z 1, 2 001 idcode 010 sample-z 1, 2 011 private 5 100 sample 4 101 private 5 110 private 5 111 bypass 3 1. places dqs in high-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the ?rst id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift dr state. 4. sample instruction does not place dqs in high-z. 5. this instruction is reserved for the exclusive use of ibm. invoking this instruction will cause improper sram functionality.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 25 boundary scan order (128k x 36), (256k x 36) (ph = place holder) exit order signal bump # exit order signal bump # exit order signal bump # 1 m2 5r 25 dq12 6f 49 dq26 2h 2 sa 4p 26 dq13 7e 50 dq25 1h 3 sa 4t 27 dq11 6e 51 sbwc 3g 4 sa 6r 28 dq10 7d 52 zq 4d 5 sa 5t 29 dq9 6d 53 ss 4e 6zz7t30sa6a54 ph 1 4g 7 dq0 6p 31 sa 6c 55 ph 2 4h 8 dq1 7p 32 sa 5c 56 sw 4m 9 dq2 6n 33 sa 5a 57 sbwd 3l 10 dq4 7n 34 ph 1 (4mb), sa(8mb) 6b 58 dq34 1k 11 dq3 6m 35 sa 5b 59 dq35 2k 12 dq5 6l 36 sa 3b 60 dq33 1l 13 dq6 7l 37 ph 1 2b 61 dq32 2l 14 dq8 6k 38 sa 3a 62 dq30 2m 15 dq7 7k 39 sa 3c 63 dq29 1n 16 sbwa 5l 40 sa 2c 64 dq31 2n 17 k 4l 41 sa 2a 65 dq28 1p 18 k 4k 42 dq18 2d 66 dq27 2p 19 g 4f 43 dq19 1d 67 sa 3t 20 sbwb 5g 44 dq20 2e 68 sa 2r 21 dq16 7h 45 dq22 1e 69 sa 4n 22 dq17 6h 46 dq21 2f 70 m1 3r 23 dq15 7g 47 dq23 2g 24 dq14 6g 48 dq24 1g 1. input of ph register connected to v ss . 2. input of ph register connected to v dd
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 25 crrh2519.07 12/13/00 boundary scan order (256k x 18), (512k x 18) (ph = place holder) exit order signal bump # exit order signal bump # 1 m2 5r 27 ph 1 2b 2 sa 6t 28 sa 3a 3 sa 4p 29 sa 3c 4 sa 6r 30 sa 2c 5 sa 5t 31 sa 2a 6 zz 7t 32 dq14 1d 7 dq5 7p 33 dq15 2e 8 dq6 6n 34 dq16 2g 9 dq7 6l 35 dq17 1h 10 dq8 7k 36 sbwb 3g 11 sbwa 5l 37 zq 4d 12 k4l38 ss 4e 13 k4k39 ph 1 4g 14 g4f40 ph 2 4h 15 dq4 6h 41 sw 4m 16 dq3 7g 42 dq13 2k 17 dq2 6f 43 dq12 1l 18 dq1 7e 44 dq10 2m 19 dq0 6d 45 dq11 1n 20 sa 6a 46 dq9 2p 21 sa 6c 47 sa 3t 22 sa 5c 48 sa 2r 23 sa 5a 49 sa 4n 24 ph 1 (4mb), sa(8mb) 6b 50 sa 2t 25 sa 5b 51 m1 3r 26 sa 3b 1. input of ph register connected to v ss . 2. input of ph register connected to v dd
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 25 tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 25 crrh2519.07 12/13/00 7 x17 bga dimensions ello guvna! note: all dimensions are in millimeters indicates a1 location under?ll plate die plate 0.71 0.05 typ 0.701 0.099 under?ll 0.1778 ref structural adhesive 1 2 3 4 5 6 7 u t r p n m l k j h fg e d c b a 7.62 1.27 0.889 0.04 diam. 3.19 ref 0.84 ref 20.32 16.764 12.7 ref 0.625 .254 14.00 12.294 top view side view bottom view 22.00 2.549 0.13 solder ball
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab preliminary 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram crrh2519.07 12/13/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 25 references the following documents give recommendations, restrictions, and limitations for 2nd level attach process: double sided 4mb sram coupled cap pbga card assembly guide qualification information, including the scope of application conditions qualified, is available from your mar- keting representative. note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design.
ibm0418a81blab ibm0436a81blab ibm0418a41blab ibm0436a41blab 8mb (256kx36 & 512x18) and 4mb (128kx36 & 256kx18) sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 25 crrh2519.07 12/13/00 revision log revision contents of modi?cation 9/98 initial release. 11/98 updated package diagram. changed part numbers from rev a to b. 2/16/99 in programmable impedance output driver dc electrical characteristics on page 9: i oh = (v ddq ? 2) ? ((rq ? 5) + 5) 15% @ v oh = v ddq / 2 for: 175 w rq 350 w . i ol = (v ddq ? 2) ? (rq ? 5) 15% @ v ol = v ddq / 2 for: 175 w rq 350 w 7/13/99 corrected 7 x17 bga dimensions. added 3n speed sort. 1/12/2000 in dc electrical characteristics on page 8: i sbss changed from 120 ma to 150 ma. i sbzz changed from 65 ma to 100 ma 2/09/2000 page 14: timing updated for synchronous operation. page 11: sleep mode setup time spec added: t zvkh =1.0ns sleep mode hold time spec added: t khzx =1.0ns page 22: enhanced bga diagram. 12/05/00 in ac characteristics on page 11: t khqv changed from 1.7 to 1.6ns. added footnote 5. t avkh , t svkh , t wvkh , t dvkh spec changed from 0.5ns to 0.3ns added footnote 6. in id register definition on page 17: revision number bits (31:28) defined as 0111. made various minor editorial changes and format refinements. 12/13/00 returned ac characteristics changes made in 12/05/00 document to their previous values.
a pyright and disclaimer ? copyright international business machines corporation 1998 all rights reserved printed in the united states of america december 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both. ibm ibm logo other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warran- ties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com crrh2519.07 12/13/00

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